Emerging from more than two years of stealth development, PA Semi unveiled the PWRficient processor family - a 64-bit multicore, scalable processor line based on the Power Architecture from IBM - that delivers high performance at very low power consumption, offering up to a tenfold advantage in performance per watt over the industry.

PA Semi is headed by Dan Dobberpuhl, the acclaimed lead designer of the DEC Alpha series of microprocessors, the ultra-power-efficient StrongARM microprocessors, and the first commercial multicore processors including the SiByte 1250. The 150-strong processor, ASIC, software and systems engineering team also includes key designers of other defining processor architectures, such as Opteron, Itanium, and UltraSPARC.

"The next wave of microprocessor innovation is contingent on solving the problem of dramatically increased power consumption," said Co-founder, President and CEO, Dan Dobberpuhl. "We had to start from scratch, rethinking every step, to achieve our breakthrough performance-per-watt design. The result is a paradigm-shifting processor that has been enthusiastically received by our customers, who look forward to building a new breed of cool, efficient, yet high-performance, systems around the PWRficient processor."

DAN DOBBERPUHL Starting from scratch to achieve breakthrough performance in the processor game

The PWRficient processors address the multi-billion dollar high-performance embedded and computing markets to
redefine power, cost, and throughput efficiency in high-performance processing. The unique system-on-chip architecture and design, underpinned by 50 patents filed and pending, delivers high performance (up to 2.5GHz per-core) at phenomenally low power consumption. In terms of performance per watt, the defining metric for all next- generation processors, PWRficient is up to 10 times superior to the competition. For example, the first PWRficient processor, a dual-core chip running at 2GHz,
dissipates just 5-13 watts typical, depending upon the application.

Beyond performance per watt, the PWRficient processor delivers key breakthroughs in cost and throughput efficiency. PWRficient processors are the first processors in their class to integrate what is typically a three - to five-chip-set platform into a single chip, called a 'platform processor'. Not only does the integration of the cores, memory, south bridge, and high-speed I/O onto one chip dramatically reduce the cost of silicon and power consumption, but it also delivers high throughput at low latency.

Through its unique modular architecture, which allows the number of cores, memory controllers, cache, serdes lanes, and protocols to easily scale, PA Semi will deliver a family of PWRficient processors targeting a variety of applications, including high-performance computing, embedded datacom and telecom, storage, and other embedded consumer applications.

The first PWRficient chip, the PA6T-1682M, which dissipates between just 5-13 watts, depending upon the application, is a dual-core implementation running at 2GHz with two DDR2 memory controllers, 2MB of L2 cache, and a flexible I/O subsystem that supports eight PCI Express controllers, two 10 Gigabit Ethernet XAUI controllers, and four Gigabit Ethernet SGMII controllers sharing 24 serdes lanes. It will sample in the third calendar quarter of 2006, with single-core and quad-core versions due in early and late 2007, respectively, and an eight-core version planned for 2008.

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